1. Field of the Invention
The present invention relates to radio frequency (RF) power transistors and more particularly to the biasing of RF power transistors.
2. Description of the Prior Art
In today""s communications systems, it is highly desirable to use linear RF amplifiers that can operate with high power efficiency and low distortion. As is well known, these RF amplifiers include cascaded RF power transistors to provide multiple stages of amplification.
There are presently various classes of RF amplifiers where each class is characterized by a particular efficiency and distortion level. For example, class A amplifiers are characterized by a low power efficiency and, of all the amplifier classes, introduce the least distortion. Class AB amplifiers are more efficient but introduce more distortion. RF amplifiers with high efficiency such as class AB amplifiers are typically useful because of their increased efficiency.
One concern related to the use of high efficiency RF amplifiers is their inherent non-linearity. There are presently various conventional methods that can be used to increase linearity in RF amplifiers and thereby reduce the amount of distortion introduced. One conventional method of linearizing RF amplifiers consists of using feedback. With feedback, RF amplifiers can be linearized simply and inexpensively. However, as is well known, the amount of linearization or reduction in distortion achievable is limited by various feedback delays.
Feedforward is another method by Which RF amplifiers can be linearized. This linearization approach consists of canceling the distortion of the RF amplifier at the output. More specifically, the distortion introduced by the RF amplifier is measured with an error signal produced by comparing the RF amplifier output signal with the input signal. After suitable scaling and delay matching, this error signal is applied to the RF amplifier output to reduce the distortion introduced by the RF amplifier. However, as is well known, this linearization method reduces the efficiency and increases the: bulkiness of the RF amplifier.
A more desirable method of linearizing an RF amplifier consists of predistorting the input signal of the RF amplifier so that at the output, the distortion introduced in the RF amplifier is cancelled. According to this method, in order to effectively predistort a signal input to an RF amplifier to cancel out the distortion introduced in the RF amplifier, the distortion characteristics or behavior of the RF amplifier must be measurable. As is well known, there are various types of distortion, which can be introduced by an RF amplifier such as for example, amplitude-to-amplitude (AM/AM) modulation and/or amplitude-to-phase (AM/PM). Generally, these types of disortion can be quantified with some confidence to determine the appropriate pre-distortion necessary at the RF amplifier input.
One exception to this however is hysteresis. Hysteresis is a particular type of distortion that arises at RF operations including operations at and beyond ultra high frequencies (UHF). Hysteresis is a distortion behavior inherent to most RF amplifiers that cannot be easily quantified or cancelled with conventional predistortion techniques. In conventional RF amplifiers, hysteresis causes distortion in proportion to the rate of change of the input signal being amplified. For example, the amount of hysteresis introduced in an input signal may at any given time depend on the recent history of the signal, the rate at which the signal operates or whether the input signal is on a rising edge or a falling edge.
Because the hysteresis introduced changes dynamically in sympathy with the rate of change of the signal being amplified, it becomes virtually impossible to predict the hysteresis behavior in an RF amplifier and predistort an input signal so as to cancel the related distortion introduced.
It has been observed that a major cause of hysteresis in a conventional RF amplifier arises from bias circuitry used to bias the RF power transistors in the amplifier. As is well known, the bias circuitry of an RF power transistor is used to feed a DC current supply to a drain/collector or gate/base terminal of the RF power transistor so that the transistor can operate. Generally, the DC current the RF power transistor draws is a function of the amplitude of the input signal. Because of this dependency and the fact that the reactive impedance of the bias circuit is non-zero, hysteresis is introduced in the output signal. To minimize this distortion, it becomes highly desirable to design the bias circuitry impedance with the lowest possible reactance at low frequencies (ideally zero) such that DC current can be applied to the RF power transistor without affecting the signal being amplified.
However, at RF frequencies, the bias circuit impedance also has an effect on the transistor output and input impedance. In most cases, impedance matching networks will be used at both the input and the output of an RF power transistor to match the transistor input and output impedance with external components. For example, an output impedance matching network will be used to match the relatively low output impedance of the RF power transistor at RF frequencies to the higher one of external circuits which, according to current microwave practice is typically 50 ohms. Because the impedance of the bias circuit impacts on the transistor input and output impedance, it is also equally desirable to design the bias circuitry with a high feed impedance at RF frequencies so as not to affect any impedance matching network which may be used.
Because of these conflicting requirements, the design of bias circuits in conventional RF power transistors has always entailed a trade-off. On one hand, bias circuits must be designed with a high impedance at RF frequencies so as not to affect the transistor input and output impedance or any impedance matching circuit used. On the other hand, the bias circuits must also be designed with a low reactive impedance at low frequencies so as not to introduce any hysteresis distortion in the signal being amplified.
In conventional RF power transistors, the emphasis is usually placed on designing bias circuits with a high impedance at RF frequencies so that the transistor input and output impedance is not affected. However, by doing so, the bias circuit reactive impedance at low frequencies is also increased which therefore inevitably induces hysteresis in signals being amplified.
Therefore it would be desirable to provide RF power transistors with a biasing method and apparatus which can provide a low reactive impedance at low frequencies to reduce hysteresis without affecting the transistor input or output impedance or any impedance matching circuit which may be used.
The present invention provides a biasing method and apparatus for a radio frequency (RF) power transistor that reduces hysteresis in the RF power transistor without affecting the transistor input or output impedance or any impedance matching network that may be used. The invention can be implemented on the input or output side of any power transistor which can operate at RF frequencies including for example, bipolar junction transistors (BJT) or any type of metal-oxide semiconductor field-effect transistors (MOSFET) including laterally diffused metal-oxide semiconductor (LDMOS) transistors and gallium arsenide field effect transistors (GaAs FET).
In one embodiment, the invention is used to provide a drain bias to an LDMOS transistor in an LDMOS transistor circuit in a manner that reduces hysteresis without any impact on the LDMOS transistor output impedance. In this embodiment, the drain bias is supplied with a drain bias circuit and fed through a low RF impedance point in the LDMOS transistor circuit so that at RF frequencies, the bias circuit no longer adversely impacts the transistor output impedance.
By removing the effect of the bias circuit at RF frequencies, the bias circuit can advantageously be designed with a low reactive impedance at low frequencies without any material consequences on the transistor output impedance. As a result, with a low enough bias circuit reactive impedance, the hysteresis introduced can be substantially reduced.
According to another embodiment, the drain bias is maintained on the drain terminal and a large capacitor is used at an appropriate point in the output matching circuit to reduce hysteresis.
According to yet another embodiment, the invention is used to provide a base bias to a BJT transistor in a BJT transistor circuit in a manner which reduces hysteresis without any impact on the BJT transistor input impedance. In this embodiment, the base bias is supplied with a base bias circuit and fed through a low RF impedance point in the BJT transistor circuit so that at RF frequencies, the base bias circuit no longer adversely impacts the transistor input impedance. Again, by removing the effect of the base bias circuit at RF frequencies, the base bias circuit can advantageously be designed with a low reactive impedance at low frequencies to reduce hysteresis without any material consequences on the transistor input impedance.
Because hysteresis in RF power transistors can be considerably reduced on both the input and output side, RF amplifiers which use RF power transistors can advantageously be linearized with predistortion techniques which are more cost-effective and simple than other linearization techniques and which in turn reduce the cost, complexity and bulkiness of RF amplifiers.
According to still another embodiment, the invention is used to provide one or more auxiliary bias feeds to a previously manufactured bias feed network of a BJT transistor in a BJT transistor circuit (or some similar transistor and circuit) in a manner which reduces hysteresis.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.